Verilog elementary tutorial (18) functions and tasks in Verilog

Li Rui Bowen 2020-11-13 10:25:08
verilog elementary tutorial functions tasks


Preface

Functions and tasks are common syntax in simulation , But fair use can also be used in design , It can be integrated .

Text

function

A lot of times we find that some code is repetitive , stay RTL Is called multiple times in . Most of them don't consume simulation time , Complex calculations may involve , It needs to be done with different data values . under these circumstances , We can declare a function , Put the duplicate code in the function , Let it return the result . This will greatly reduce RTL The number of lines in , Because now all you need to do is make a function call , And pass the data that needs to be calculated on it . in fact , This is related to C The functions in the language are very similar .

The purpose of the function is to return a value to be used in an expression . A function definition is always defined by keywords function Start , And then Return type name And in brackets Port list . When Verilog find endfunction When a keyword , I know that a function definition is over . Be careful , A function must declare at least one input , If the function doesn't return anything , The return type is void.

grammar

function [automatic] [return_type] name ([port_list]);
[statements]
endfunction

keyword automatic Will cause the function to be reentrant , Items declared in tasks are dynamically assigned , Instead of sharing between different calls to a task . This is for recursive functions , And when the same function is forked by N Concurrent processes , Will be very useful .

Function declaration

There are two ways to declare the input to a function .

function [7:0] sum;
input [7:0] a, b;
begin
sum = a + b;
end
endfunction
function [7:0] sum (input [7:0] a, b);
begin
sum = a + b;
end
endfunction

Returns a value from a function

The function definition implicitly creates an internal variable with the same name as the function . therefore , It is illegal to declare another variable with the same name in the scope of a function . The return value is initialized by assigning the result of the function to an internal variable .

sum = a + b;

Function call

A function call is an operand with an expression , The syntax is shown in the figure below .

reg [7:0] result;
reg [7:0] a, b;
initial begin
a = 4;
b = 5;
#10 result = sum (a, b);
end

Function rules

  • Function cannot contain any time controlled statements , Such as #, @, wait, posedge, negedge
  • Function cannot call task , Because it may consume simulation time , But you can call other functions .
  • Function should have at least one input
  • Function cannot have a nonblocking assignment or force…release or assign…deassign.
  • Function cannot have any triggers
  • Functions cannot have output perhaps inout

Mission

The function is used to process input , And return a single value , And tasks are more general , It can calculate multiple result values , And use output and inout Parameters of type return . Tasks can include @、posedge Simulation time-consuming elements . There are two ways to write a task , We're going to see .

grammar


// Style 1
task [name];
input [port_list];
inout [port_list];
output [port_list];
begin
[statements]
end
endtask
// Style 2
task [name] (input [port_list], inout [port_list], output [port_list]);
begin
[statements]
end
endtask

keyword automatic Will re-enter the task , Otherwise it will default to static . If a task is static , Then all its member variables will be shared in different calls of the same task , The task has been started to run concurrently . Be careful ,auomatic Task items cannot be accessed through hierarchical references .

Task call

If the task does not require any parameters , So you can avoid using parameter lists . If the task requires parameters , You can provide parameters in the same statement when calling a task .


task sum (input [7:0] a, b, output [7:0] c);
begin
c = a + b;
end
endtask
// or 
task sum;
input [7:0] a, b;
output [7:0] c;
begin
c = a + b;
end
endtask
initial begin
reg [7:0] x, y , z;
sum (x, y, z);
end

Task enabling parameters (x,y,z) Parameters corresponding to the task definition (a,b,c). because a and b It's input ,x and y The values of will be placed in a and b in . because c Is declared as output , And in the call process with z Connect , So the sum will automatically be from c Pass to variable z in .

Overall task

Tasks declared outside of all modules are called global tasks , Because they have global scope , It can be invoked in any module .


// This task is outside all modules
task display();
$display("Hello World !");
endtask
module des;
initial begin
display();
end
endmodule

Simulation results :

Hello World !

The difference between functions and tasks

function Mission
There can't be time control statements / Delay , So it is executed in the same simulation time unit . Can contain time control statements / Delay , And only at other times .
Unable to enable task Other tasks and functions can be implemented
There must be at least one input , Functions cannot have output perhaps inout. You can have zero or more parameters of any type .
Only one value can be returned Cannot return a value , But you can use output parameters to achieve the same effect .

Looking back

Verilog Junior course (17)Verilog Medium case sentence

Verilog Junior course (16)Verilog Control block in

Verilog Junior course (15)Verilog Blocking and non blocking statements in

Verilog Junior course (14)Verilog The assignment statement in

Verilog Junior course (13)Verilog Block statements in

Verilog Junior course (12)Verilog Medium generate block

Verilog Junior course (11)Verilog Medium initial block

Verilog Junior course (10)Verilog Of always block

Verilog Junior course (9)Verilog Operator

Verilog Junior course (8)Verilog Medium assign sentence

Verilog Junior course (7)Verilog Modularization and handling of suspended ports

Verilog Junior course (6)Verilog Module and port

Verilog Junior course (5)Verilog Multidimensional arrays and memory in

Verilog Junior course (4)Verilog Scalars and vectors in

Verilog Junior course (3)Verilog data type

Verilog Junior course (2)Verilog HDL The Elementary Grammar of

Verilog Junior course (1) know Verilog HDL

Abstract layer of chip design and its design style

Verilog as well as VHDL The code principles advocated by

FPGA/ASIC Beginners should learn Verilog still VHDL?

Reference materials and recommendations

Verilog Functions

Verilog Task

WeChat official account : FPGA LAB

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本文为[Li Rui Bowen]所创,转载请带上原文链接,感谢

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