## Verilog elementary tutorial (14) assignment statements in Verilog

Li Rui Bowen 2020-11-13 10:28:17
verilog elementary tutorial assignment statements

## Preface

What are assignment statements ？ Put the value on a wire net or a variable , This operation is called assignment , english ：assignment.
It has three basic forms ：

• Procedural assignment
• Continuous assignment
• Processes are continuously assigned values

## Text

### A reasonable left value

An assignment statement has two parts – Right value （RHS） And l-value （LHS）, There is an equal sign in the middle （=） Or a sign less than equal （<=）.
The next blog post will see ,`=` Assign a value to blocking ,`<=` Assign a non blocking value to .

In procedural assignment , A reasonable l-value should be ：

• Variable ( vector / Scalar )
• vector reg、integer or time Variable ` Bit selection ` or ` Part of the choice `.
• Memory (Memory word)
• Any combination of the above

Procedure assignment usually occurs in block statements , for example initial block ,always block , also task as well as function in .

In the continuous assignment , A reasonable l-value should be ：

• Wire network （ vector / Scalar ）
• Bit selection or partial selection of vector line network .
• A combination of bit selection and partial selection

Process continuity assignment ：

• Networks or variables （ vector / Scalar ）
• Bit selection or partial selection of line net vector

RHS It can contain any expression that evaluates to the final value , and LHS Represents a network or a variable ,RHS The value in is assigned to it .
for example ：

``````module tb;
reg clk;
reg a, b, c, d, e;
wire f, y;
reg z;
// clk is on the LHS and the not of clk forms RHS
always #10 clk = ~clk;
// y is the LHS and the constant 1 is RHS
assign y = 1;
// f is the LHS, and the expression of a,b,d,e forms the RHS
assign f = (a | b) ^ (d & e);
always @ (posedge clk) begin
// z is the LHS, and the expression of a,b,c,d forms the RHS
z <= a + b + c + d;
end
initial begin
// Variable names on the left form LHS while 0 is RHS
a <= 0; b <= 0; c <= 0; d <= 0; e <= 0;
clk <= 0;
end
endmodule
``````

### Procedural assignment （Procedural assignment）

Procedural assignment occurs in a process （procedures） in , Such as always、initial、task And functions , Used to put values on variables . The variable will hold the value , Until the next assignment to the same variable .

When the simulation executes the statement at a certain time in the simulation time , The value will be placed on the variable . This can be done by using control flow statements , Such as if-else-if、case Statement and loop mechanism to control and modify the way we want .

``````reg [7:0] data;
integer count;
real period;
initial begin
data = 8'h3e;
period = 4.23;
count = 0;
end
always @ (posedge clk)
count <= count + 1;
``````

Variable declaration assignment

An initial value can be placed on a variable when it is declared , As shown in the figure below . This assignment has no duration , And keep this value until the next assignment to the same variable occurs .

` Be careful , Assignment of a variable declaration to an array is not allowed .`

``````module my_block;
initial begin
#20 data = 32'h1234_5678; // data will have dead_cafe from time 0 to time 20
// At time 20, data will get 12345678
end
endmodule
``````
``````reg [3:0] a = 4'b4;
// is equivalent to
reg [3:0] a;
initial a = 4'b4;
``````

If the variable is in the declaration process and initial Time in the block 0 Initialized , As shown in the following example , The order of assignment is not guaranteed , So variable values can have 8’h05 or 8’hee.

``````module my_block;
initial
endmodule
``````

This is not recommended , Normal people don't do this .

``````reg [3:0] array [3:0] = 0; // illegal
integer i = 0, j; // declares two integers i,j and i is assigned 0
real r2 = 4.5, r3 = 8; // declares two real numbers r2,r3 and are assigned 4.5, 8 resp.
time startTime = 40; // declares time variable with initial value 40
``````

### Continuous assignment

This is used to assign values to scalar and vector nets , as long as RHS Change will happen . It provides a way to model combinatorial logic without specifying the interconnection of gates , And make it easier to drive the network with logical expressions .

``````// Example model of an AND gate
wire a, b, c;
assign a = b & c;
``````

whenever b or c When the value of changes ,RHS The entire expression in will be evaluated ,a Will be updated with the new value .

Be careful ： We can still assign values continuously when we declare online , for example ：

``````wire penable = 1;
``````

But we have to use it with caution , Because a net can only declare once , So a net can only have one declaration assignment .

in other words , Once we're declaring wire Variables are assigned continuously , The following cannot be assigned continuously , Otherwise, it's multi drive .

### Process continuity assignment

This type of assignment seems rarely heard of , But there is .
There are two types of ：

• `assign ... deassign`
• `force ... release`

assign … deassign

This will override all procedural assignments of variables , And through the use of and deassign The same signal to stop . The value of the variable will remain unchanged , Until the variable gets a new value through procedural or procedural continuous assignment . Of the assignment statement LHS It can't be a choice 、 Partial selection or array reference , But it can be a variable or a connection of variables .

``````reg q;
initial begin
assign q = 0;
#10 deassign q;
end
``````

In order to test , I simulated it , Simulation file ：

``````module assign_tb();
reg q;
initial begin
assign q = 0;
#10 deassign q;
#10 q = 1;
#10 \$finish;
end
endmodule
``````

According to the grammar , It should be before 20ns All remain as assign assignment 0, For after 1;

The simulation results show that the same is true .

force…release

These sentences are related to assign… deassign Statements like , But it can also be applied to nets and variables .LHS It can be bit selection of the net 、 Part of the choice of the net 、 Variables or nets , But it can't be a reference to an array or a bit of a variable / Part of the choice .force Statement will override all other assignments to variables , Until you release it with the release keyword .

``````reg o, a, b;
initial begin
force o = a & b;
...
release o;
end
``````

In order to test , We design the following simulation files ：

```````timescale 1ns / 1ps
//
// Engineer:reborn lee
// Create Date: 2020/07/18 17:36:02
// Module Name: assign_tb
//
module assign_tb();
reg o, a = 1, b = 1;
initial begin
force o = a & b;
#10 a = 0;
b = 0;
o = 1;
#10 a = 1;
b = 1;
o = 0;
#20 release o;
#10
a = 1;
b = 1;
o = 0;
#10
a = 0;
b = 1;
o = 1;
#10 \$finish;
end
endmodule
``````

Now analyze this simple test program ：
At the beginning , because a and b The initial values of are 1, also ：

`````` force o = a & b;
``````

therefore ,o The value of is 1;
after 10ns,a and b The value of is assigned to 0, therefore o Should be 0, But now ：

``````// force o = a & b;
#10 a = 0;
b = 0;
o = 1;
``````

We try to o pull up ;
Also in the past 10ns：

``````//initial begin
// force o = a & b;
//#10 a = 0;
//b = 0;
//o = 1;
#10 a = 1;
b = 1;
o = 0;
``````

Let's try again o Pull it down ;
As can be seen from the following simulation diagram, they are all successful .

This explanation , stay release Before , The variable o All operations of are ignored .

Continue to look at , stay release after , We are right. o All operations are successful ：

## Looking back

Verilog Junior course （13）Verilog Block statements in

Verilog Junior course （12）Verilog Medium generate block

Verilog Junior course （11）Verilog Medium initial block

Verilog Junior course （10）Verilog Of always block

Verilog Junior course （9）Verilog Operator

Verilog Junior course （8）Verilog Medium assign sentence

Verilog Junior course （7）Verilog Modularization and handling of suspended ports

Verilog Junior course （6）Verilog Module and port

Verilog Junior course （5）Verilog Multidimensional arrays and memory in

Verilog Junior course （4）Verilog Scalars and vectors in

Verilog Junior course （3）Verilog data type

Verilog Junior course （2）Verilog HDL The Elementary Grammar of

Verilog Junior course （1） know Verilog HDL

Abstract layer of chip design and its design style

Verilog as well as VHDL The code principles advocated by

FPGA/ASIC Beginners should learn Verilog still VHDL？

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