## Verilog elementary course (7) Verilog module instantiation and handling of suspended ports

Li Rui Bowen 2020-11-13 10:28:35
verilog elementary course verilog module

## Write it at the front

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## Text

Verilog There are two ways of instantiation , One is to instantiate according to the order of port definition , One is to instantiate by port name .
The following will bring the narration and comparison of these contents , And how to deal with empty ports .

### Serial port connections

Sequential port connections are the first way to instantiate , Not recommended , But you have to know , Because there's still some code that uses this instantiation .

as follows , If I design a module ：

module mydesign ( input x, y, z, // x is at position 1, y at 2, x at 3 and
output o); // o is at position 4
endmodule

So, if you instantiate by port order , As shown below ：

module tb_top;
wire [1:0] a;
wire b, c;
mydesign d0 (a[0], b, a[1], c); // a[0] is at position 1 so it is automatically connected to x
// b is at position 2 so it is automatically connected to y
// a[1] is at position 3 so it is connected to z
// c is at position 4, and hence connection is with o
endmodule

### Port connections by name

Or follow the example above , I ordered a module ：

module mydesign ( input x, y, z, // x is at position 1, y at 2, x at 3 and
output o); // o is at position 4
endmodule

If you instantiate by port name , as follows ：

module tb_top;
wire [1:0] a;
wire b, c;
mydesign d0(
.x(a[0]),
.y(b),
.z(a[1]),
.o(c)
);
endmodule

We recommend instantiation by name , Because it doesn't take order , Not easy to make mistakes .
Software or plug-ins that automatically generate instantiated templates , Almost all of them generate this kind of instantiation template . If you generate templates that are instantiated sequentially , It's doomed to be yellow .

These are not the focus , The point is the next topic , We often look at the ports that are not connected when we do actual projects , How do we think ？ Or how to deal with it ？

### Unconnected / Dangling port processing

Ports not connected to the instantiation module are treated as high impedance states . as follows ：

Take the module designed above as an example ：

module mydesign ( input x, y, z, // x is at position 1, y at 2, x at 3 and
output o); // o is at position 4
endmodule

We use this module as an example ：

module design_top(
input [1:0] a,
output c
);
mydesign d0 ( // x is an input and not connected, hence a[0] will be Z
.y (a[1]),
.z (a[1]),
.o ()); // o has valid value in mydesign but since
// it is not connected to "c" in design_top, c will be Z
endmodule

You can see the port x, I didn't even write , therefore , Think of it as an unconnected dangling port , It's a high resistance state ;
port o, Although I wrote it , But it is not connected to any port in the top module , So the top port c It's also a high resistance state .

Here is an example of a shift register , Look at some ports that are not connected , What does the generated hardware schematic look like .

// Module called "dff" has 3 inputs and 1 output port
module dff ( input d,
input clk,
input rstn,
output reg q);
// Contents of the module
always @ (posedge clk) begin
if (!rstn)
q <= 0;
else
q <= d;
end
endmodule

Shift registers are formed by instantiating triggers , Shift register if the ports are connected ：

module shift_reg ( input d,
input clk,
input rstn,
output q);
wire [2:0] q_net;
dff u0 (.d(d), .clk(clk), .rstn(rstn), .q(q_net[0]));
dff u1 (.d(q_net[0]), .clk(clk), .rstn(rstn), .q(q_net[1]));
dff u2 (.d(q_net[1]), .clk(clk), .rstn(rstn), .q(q_net[2]));
dff u3 (.d(q_net[2]), .clk(clk), .rstn(rstn), .q(q));
endmodule

RTL Schematic diagram ：

If some ports are not connected ：

module shift_reg ( input d,
input clk,
input rstn,
output q);
wire [2:0] q_net;
dff u0 (.d(d), .clk(clk), .rstn(rstn), .q(q_net[0]));
dff u1 (.d(q_net[0]), .clk(clk), .rstn(rstn), .q()); // Output q is left floating
dff u2 (.d(q_net[1]), .clk(clk), .rstn(rstn), .q()); // Output q is left floating
dff u3 (.d(q_net[2]), .clk(clk), .rstn(rstn), .q(q));
endmodule

RTL The schematic diagram is ：

In the simulation , Because the port is hanging , therefore , The output is also in a high impedance state z.

### Description of the module port

All port declarations are implicitly declared as wire, So in this case, the port direction is enough . However, the output port that needs to store the value should be declared as reg data type , And it can be used in program blocks , such as always and initial only.

Enter or inout Port of type cannot be declared as reg, Because they are continuously driven from the outside , Values should not be stored , It's about reflecting changes in external signals as soon as possible . It's perfectly legal to connect two ports of different vector sizes , But take the port with smaller vector size , The remaining bits of the other wide port will be ignored .