Verilog elementary tutorial (4) scalar and vector in Verilog

Li Rui Bowen 2020-11-13 10:28:40
verilog elementary tutorial scalar vector



Write it at the front

Last blog post That's it Verilog Data type of , One of the most commonly used is reg Type and wire type , These two types can define one bit variable or multi bit variable , One of them is called a scalar , Many bits are called vectors , It's like an array . This blog is mainly about the operation of multiple variables .
for example :
Verilog 2001 The revised edition added bit Bit selection grammar :

[<start_bit> +: <width>] // part-select increments from start-bit
[<start_bit> -: <width>] // part-select decrements from start-bit
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Scalars and variables

Verilog Need to represent a single bit and a group of multiple bits . for example , A single bit The timing element is a trigger . But one 16 The bit timing element is one that can hold 16 Bit register . So ,Verilog There are scalar and vector nets and variables .
One with no specified range net or reg The statement is considered to be 1 A wide , It's a scalar . If a range is specified , that net or reg It becomes a multi bit entity , It's called a vector .

 Scalars and vectors

 wire o_nor; // single bit scalar net
wire [7:0] o_flop; // 8-bit vector net
reg parity; // single bit scalar variable
reg [31:0] addr; // 32 bit vector variable to store address

Ranges provide the ability to address individual bits in a vector . The highest bit of the vector should be specified as the left-handed value in the range , And the lowest bit of the vector should be assigned to the right side .

 wire [msb:lsb] name;
integer my_msb;
wire [15:0] priority; // msb = 15, lsb = 0
wire [my_msb: 2] prior; // illegal

In the example above , Will create a 16 Bit wide net , It's called priority . Be careful ,msb and Isb It should be a constant expression , You can't use variables instead .
notes :msb as well as lsb It can be any integer value – Plus or minus or zero , and Isb Can be greater than 、 Equal to or less than msb Value . But in order to keep the style uniform , That is, the value on the left is larger than the value on the right , So I don't recommend lsb Greater than or equal to msb.

Bit selection

Any bit in a vector can be selected individually , And you can assign it a separate value .
Such as :

 reg [7:0] addr; // 8-bit reg variable [7, 6, 5, 4, 3, 2, 1, 0]
addr [0] = 1; // assign 1 to bit 0 of addr
addr [3] = 0; // assign 0 to bit 3 of addr

Schematic diagram after operation :

 single bit choice

But not beyond the vector index range :

 addr [8] = 1; // illegal : bit8 does not exist in addr

Single bit selection , Of course, you can also choose the scope , That is to say, the adjacent bits are continuously selected for assignment and other operations .
for example :

reg [31:0] addr;
addr [23:16] = 8'h23; // bits 23 to 16 will be replaced by the new value 'h23 -> constant part-select

 Multiple choices

There are many choices above , Constant is used as index value .
You can also use the following methods :

[<start_bit> +: <width>] // part-select increments from start-bit
[<start_bit> -: <width>] // part-select decrements from start-bit

Have a variable partial selection , You can use it effectively in a loop to select parts of a vector . Although the start bit can be changed , But the width has to be constant .

for example :

module des;
reg [31:0] data;
int i;
initial begin
data = 32'hFACE_CAFE;
for (i = 0; i < 4; i++) begin
$display ("data[8*%0d +: 8] = 0x%0h", i, data[8*i +: 8]);
end
$display ("data[7:0] = 0x%0h", data[7:0]);
$display ("data[15:8] = 0x%0h", data[15:8]);
$display ("data[23:16] = 0x%0h", data[23:16]);
$display ("data[31:24] = 0x%0h", data[31:24]);
end
endmodule

Simulation results :

ncsim> run
data[8*0 +: 8] = 0xfe // ~ data [8*0+8 : 8*0]
data[8*1 +: 8] = 0xca // ~ data [8*1+8 : 8*1]
data[8*2 +: 8] = 0xce // ~ data [8*2+8 : 8*2]
data[8*3 +: 8] = 0xfa // ~ data [8*3+8 : 8*3]
data[7:0] = 0xfe
data[15:8] = 0xca
data[23:16] = 0xce
data[31:24] = 0xfa
ncsim: *W,RNQUIE: Simulation is complete.

Common mistakes

give an example :

module tb;
reg [15:0] data;
initial begin
$display ("data[0:9] = 0x%0h", data[0:9]); // Error : Reversed part-select index expression ordering
end
endmodule

This common mistake , It's a mixture of msb as well as lsb It's the style of , Again , Uniform style ,msb Doing it ,lsb On the right !


Reference material


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